This invention is related to an integrated circuit device and more particularly to electrical interconnections in a ball grid array package.
As the semiconductor industry moves toward higher circuit density, the number of input/output pins and the operating speed of the devices is increasing dramatically, as well as the number of circuits with more than one operating voltage. In order to minimize the complexity and the area of circuit boards required for these high pin count, multiple power supply devices, the integrated circuit packages are constructed with multilayer power and ground planes which can reduce pin count by providing common contacts for several inputs and outputs, and can allow improved electrical and thermal performance of the device.
In response to the demand for IC packages of higher lead count and smaller foot print, Ball Grid Array (BGA) packages continue to be developed. A BGA package is a surface mount package which is assembled to an external circuit board using an array of solder balls confined within the area of the package. An example of a BGA package is given in FIG. 1. Typically the BGA package 100 is in a xe2x80x9ccavity upxe2x80x9d configuration, indicating that the semiconductor chip 101 is attached to the top surface 103a (i.e., upward facing surface) of the substrate 103, and that solder balls 105 which interconnect the package to a printed wiring board are attached to the back side 103b (i.e., downward facing surface) of the substrate. The chip is electrically interconnected to traces on the substrate by wire bonding or by flip chip bump connections 107, as shown in FIG. 1. A lid 108 or other form of encapsulation covers the chip and provides mechanical and environmental protection.
Substrates of high performance and high pin count BGAs have multiple layers of metal traces separated by dielectric layers and connected through vias to provide power and ground planes, and these structures will be discussed in more detail later. Typically, a separate conductor and dielectric layer is required for each input/output function, such as a contact layer with routing for signal, power and ground, a ground plane, a power plane for each operating voltage, and a layer for the external contacts. Limitations of prior art BGA packages are low thermal dissipation, electrical performance limited by the number of conductor layers, and associated costs of substrates with multiple metal and dielectric layers, and package reliability and susceptibility to moisture.
The electrical performance and thermal dissipation of a BGA package can be significantly enhanced by a xe2x80x9ccavity downxe2x80x9d BGA package. A xe2x80x9ccavity downxe2x80x9d BGA package typically has a die cavity in a multilayer printed circuit board (PCB) substrate. The multilayer substrate allows lower parasitic impedance, and inclusion of a metal slug at the bottom of the cavity increases thermal dissipation of the package. A chip cavity or recess in the package is required to allow sufficient clearance for the chip and its interconnecting wire bonds when the package has been assembled onto a printed wiring board.
A xe2x80x9ccavity downxe2x80x9d BGA package can also be fabricated using a substrate with multilayer PCB technology. Both xe2x80x9ccavity upxe2x80x9d and xe2x80x9ccavity downxe2x80x9d BGA packages using such substrates suffer from high cost, and as the pin count increases, the limitations of PCB printing technology force larger package sizes with increased inductance resulting from the longer conductor length.
In an attempt to provide a substrate with higher circuit density and to allow assembly of high pin count devices, a TGA (TAB Grid Array) package 200 was disclosed and a cross section is shown in FIG. 2. The TGA uses a TAB (Tape automated bond) flexible tape 202 with fine line interconnections for inner lead bonding of the tape conductors to bumps on the chip. The flexible tape 202 has a dielectric layer 209 and 210 on either side of the metal 203a layer with traces which provide interconnection between the chip contacts and solder balls 211 on the package. The tape is attached by an adhesive 208 to a stiffener 206 with a cavity for housing the semiconductor chip 201. The chip is protected by an encapsulating material 204. Solder balls 211 for external connection are attached to the interconnection traces, and in selected locations 213 to the stiffener which acts like a ground plane. While this approach has merits, it is based on TAB or wire bonding of the die, both of which are limited to perimeter bonded integrated circuit chips, and may not be acceptable for very high pin count devices. In addition, TAB bonding has not proved to be an industry accepted, production worthy process, largely because of high costs. Wire bonding adds inductance to the circuit and becomes a limiting feature for very high performance and high pin count devices.
More advanced integrated circuits are being designed with flip chip interconnections. These circuits often require reliable, high performance BGA packages to support the emerging trends of flip chip interconnection and of chips having multiple operating voltages.
In accordance with the preferred embodiment of the present invention, a cavity down BGA package is provided comprising a flip chip interconnected integrated circuit, a stiffener or package base, an interposer circuit having two conductive metal layers separated by a dielectric layer, and a frame which serves the dual purposes of providing electrical interconnection between the interposer circuit and the external solder ball terminals, and a cavity for housing the integrated circuit chip.
Routing for signal, power and ground contacts, including one or more power and ground planes are provided on the interposer circuit. Metallization on the first surface of the interposer circuit provides routing from the flip chip terminals of the integrated circuit to power planes and /or bus structures, to external bump contacts, and through vias to the ground plane on the second metal layer. Through the use of specific boundaries multiple power buses and planes on the same metal layer are achieved, thus supporting a need for packaging an integrated circuit with multiple operating voltages.
Contact pads with solder bumps on the first surface of the interposer circuit correspond to metallized vias in the frame. The solder bumps provide both mechanical and electrical contact between the interposer circuitry and the external solder ball contacts. The second surface of interposer circuit is adhered to the stiffener. Integrity of the small bumps which provide contact between the interposer and stiffener base and the frame, as well as the flip chip bumps on the integrated circuit is enhanced by underfill materials designed to absorb thermal and mechanical stresses between dissimilar materials of the package. External solder ball terminals are connected to the frame and contact the flex circuit through vias in the frame. The cavity of the package is filled with a polymeric compound for environmental and mechanical protection.
In an alternate embodiment, an interposer circuit having electrical routing for signal, power and ground contacts accomplished on two conductor layers through selective planes and buses with specific boundaries is assembled in a cavity up BGA configuration.